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MIPS instruction set
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#	Item
61	Preliminary Product Brief SR1 64-bit Superscalar Embedded RISC CPU Core OVERVIEW Add to Reading List Source URL: davesource.com Language: English - Date: 2003-06-17 04:34:07 Instruction set architectures Parallel computing Digital signal processing R5000 MIPS architecture Multi-core processor Superscalar Central processing unit R8000 Computer architecture Computing Computer hardware
62	______________QuicKit RISC Modules _ __________ MIPS PM4700 MIPS PM5000 Add to Reading List Source URL: www.cacdsp.com Language: English - Date: 2001-12-11 11:09:04 Instruction set architectures MIPS Technologies MIPS architecture R4600 R4000 Reduced instruction set computing R5000 64-bit CPU cache Computer hardware Computer architecture Computing
63	__ __________________VME - QuicKit Telephony - Ethernet_ QuicKit Telephony 6QH5420E Add to Reading List Source URL: www.cacdsp.com Language: English - Date: 2002-02-07 11:36:02 Electronics Electronic engineering Computer buses Electronics manufacturing Joint Test Action Group VMEbus MIPS architecture H.100 GreenSpring Computers IEEE standards Computer architecture Instruction set architectures
64	Vector IRAM A Media-enhanced Vector Processor with Embedded DRAM Christoforos Kozyrakis, Joseph Gebis, David Martin, Samuel Williams, Ioannis Mavroidis, Steven Pope, Darren Jones, and David Patterson Add to Reading List Source URL: www.hotchips.org Language: English* - Date: 2013-07-27 23:38:22 Computer hardware Vector processor Processor register MIPS architecture CPU cache Instruction set Joint Test Action Group Computer architecture Central processing unit Computing
65	__ ___________________________VME – QuicKit Telephony_ The modular design of our QuicKit product line makes it possible to prototype high-performance, Add to Reading List Source URL: www.cacdsp.com Language: English - Date: 2002-06-04 16:04:39 IEEE standards Instruction set architectures MIPS architecture VMEbus Computing Backplane GreenSpring Computers MIPS Magnum Computer buses Computer architecture MIPS Technologies
66	Microsoft Word - 19-Final-Code-Generation.doc Add to Reading List Source URL: dragonbook.stanford.edu Language: English - Date: 2008-09-08 17:20:29 Subroutines Instruction set architectures Central processing unit MIPS architecture Assembly languages Calling convention Call stack Processor register Stack Computing Computer architecture Software engineering
67	™ The SB-1 Core: TM A High Performance, Add to Reading List Source URL: www.hotchips.org Language: English - Date: 2013-07-27 23:38:17 Central processing unit Instruction set architectures Microprocessors MIPS architecture CPU cache Microarchitecture Classic RISC pipeline Computer architecture Computer hardware Computer engineering
68	HC17.S5T2 The Design and Implementation of the TRIPS Prototype Chip.ppt Add to Reading List Source URL: www.hotchips.org Language: English - Date: 2013-07-27 23:47:27 Central processing unit Microprocessors Computer memory Explicit Data Graph Execution CPU cache Instruction set Microarchitecture Simultaneous multithreading MIPS architecture Computer architecture Computer hardware Computer engineering
69	__ ___________compactPCI - QuicKit Telephony – 6QC6202_ QuicKit Multi – channel: 6QC6202 Add to Reading List Source URL: www.cacdsp.com Language: English - Date: 2002-01-03 12:19:13 Electronics Electronics manufacturing Joint Test Action Group MIPS architecture Computing CompactPCI Evaluation Instruction set architectures MIPS Technologies Computer buses
70	__ ______________________VME - QuicKit Telephony - ATM_ QuicKit ATM PN:6QH5420A Add to Reading List Source URL: www.cacdsp.com Language: English - Date: 2001-12-07 17:27:39 Electronic engineering Instruction set architectures Integrated circuits Electronics manufacturing Joint Test Action Group MIPS architecture VMEbus PHY IEEE standards Electronics Computer architecture

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